GATE CSE 2014 SET-3
Q31.
In the following pairs of OSI protocol layer/sub-layer and its functionality, the INCORRECT pair isQ32.
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (Ex), memory access (MEM), and register write back (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the Ex stage is split into two stages (Ex1, Ex2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the Ex stage and produce the next instruction pointer at the end of the Ex stage in the old design and at the end of the Ex2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is __________Q33.
With respect to the numerical evaluation of the definite integral,K=\int_{a}^{b}x^{2}dx , where a and b are given, which of the following statements is/are TRUE? (I) The value of K obtained using the trapezoidal rule is always greater than or equal to the exact value of the definite integral. (II) The value of K obtained using the Simpson's rule is always equal to the exact value of the definite integral.Q34.
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns. Which processor has the highest peak clock frequency?Q35.
Let \delta denote the minimum degree of a vertex in a graph. For all planar graphs on n vertices with \delta \geq 3, which one of the following is TRUE?Q36.
Let S be a sample space and two mutually exclusive events A and B be such that A\cupB = S. If P(.) denotes the probability of the event, the maximum value of P(A)P(B) is ______Q37.
An IP router with a Maximum Transmission Unit (MTU) of 1500 bytes has received an IP packet of size 4404 bytes with an IP header of length 20 bytes. The values of the relevant fields in the header of the third IP fragment generated by the router for this packet areQ38.
Host A (on TCP/IP v4 network A) sends an IP datagram D to host B (also on TCP/IP V4 network B). Assume that no error occurred during the transmission of D. When D reaches B, which of the following IP header field(s) may be different from that of the original datagram D? (i) TTL (ii) Checksum (iii) Fragment OffsetQ39.
Consider the following statements: P: Good mobile phones are not cheap Q: Cheap mobile phones are not good L: P implies Q M: Q implies P N: P is equivalent to Q Which one of the following about L, M, and N is CORRECT?